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| Categories | Single Layer Capacitor |
|---|---|
| Temperature Coefficient (TCC): | ±15% (X7R) / 0±30 ppm/℃ (NPO) |
| Quality Factor (Q-Value): | Min. 1000 @ 1 MHz |
| Substrate Doping Concentration: | 1e15 cm^-3 |
| Model Number: | HACC101S10V500 |
| Breakdown Voltage: | 10 V |
| Interface Trap Density: | 1e10 cm^-2 eV^-1 |
| Brand Name: | Hoan |
| Place of Origin: | china |
| Dielectric Constant (K): | High-K (e.g., K=140) / Low-K |
| Payment Terms: | L/C,D/A,D/P,T/T, |
| MOQ: | 10 |
| Dissipation Factor (DF / Tan δ): | ≤0.15% @ 1 kHz, 1Vrms |
| Company Info. |
| HongAn Microwave Co., Ltd. |
| Verified Supplier |
| View Contact Details |
| Product List |
HACC101S10V500 Double-Sided Bordered SLC (100pF,50V)
What is a Double-Sided Bordered Single Layer Capacitor?
For high-reliability microelectronic packaging, securing both the
top and bottom of a chip capacitor is critical. The HACC101S10V500
is designed as a Double-Sided Bordered (Margin) Single Layer
Capacitor.
Unlike single-bordered variants, this chip features an un-metallized, exposed ceramic border (Margin) on both the top and bottom surfaces.
•Top Margin: Prevents gold wire-bonding short circuits from accidental
alignment drifts.
•Bottom Margin: Prevents conductive silver epoxies (e.g., H20E) from migrating up
the vertical sidewalls of the chip during bottom die attachment.
This dual-barrier architecture guarantees that even under automated, high-volume production, the rate of epoxy-induced short-circuiting is reduced to absolute zero.
The Science Behind TaN/TiW/Ni/Au Thin-Film Metallization
The HACC101S10V500 stands out due to its multi-layer TaN/TiW/Ni/Au (Tantalum Nitride / Titanium-Tungsten / Nickel / Gold) metallization on both electrodes (thickness ≥ 2.5 µm Min). Here is why this complex film system is critical for microwave modules:
1.TaN (Tantalum Nitride) Layer: Serves as an ultra-robust adhesion layer, locking the
metallization to the ceramic dielectric body and preventing
electrode peeling under high-temperature baking.
2.TiW (Titanium-Tungsten) Barrier: Blocks the diffusion of copper or underlying substrate materials
into the gold layer.
3.Ni (Nickel) Barrier Layer: Acts as an industry-standard anti-leaching barrier. It prevents
gold-leaching (dissolution of gold into solder or epoxies) during
high-temperature reflow or silver-epoxy curing.
4.Au (Gold) Top Coat: Offers a highly solderable, non-oxidizing surface optimized for
thermosonic gold wire bonding (Au wire-bonding), ensuring
outstanding pull-strength.
Dimensions

Technical Specifications (HACC101S10V500)
| Technical Parameter | Certified Specification Value | Test /Environmental Conditions |
| Model Number | HACC101S10V500 | |
| Capacitor Type | Single Layer Ceramic Chip (SLC) | Double-sided bordered (Margin) type |
| Capacitance Value | 100 pF ± 20% | Measured @ 1kHz, 1Vrms, 25°C, No DCBias |
| Rated Voltage | 50 V DC | Highly stable voltage handling |
| Operating Temp.Range | -55°C to +125°C | Fully compliant with aerospace standards |
| Top Film Structure | TaN/TiW/Ni/Au (> 2.5 um Min) | Excellent wire-bonding pull-strength |
| Bottom Film Structure | TaN/TiW/Ni/Au (> 2.5 um Min) | Optimized for silver epoxy die-attach |
| Compatible Assembly | Conductive Epoxy (H20E) /Soldering | Supports gold wire bonding |
Micro-Assembly & Wire Bonding Best Practices
To ensure the mechanical longevity of the HACC101S10V500 in your
hybrid microcircuits:
1.Conductive Epoxy Mounting:
•Highly optimized for conductive silver epoxy (e.g., H20E).
•Recommended Baking Profile: Cure at 120℃ for 30 minutes for
optimal shear strength and electrical conductivity.
2.Wire Bonding Landing Area:
•To prevent localized micro-fractures in the single-layer ceramic
structure, the gold-wire bonding wedge/ball must land at least 25
µm away from the gold pad’s outer edge.
3.Sidewall Inspection:
•Thanks to the double-sided margin, the bottom epoxy fillet is
safely contained. Visually inspect under a microscope to ensure no
epoxy reaches the top gold pad.
FAQ
Q1: Why is HACC101S10V500 rated at 50V while some others are 100V?
A: The 50V rating allows the use of an optimized dielectric
thickness, enabling a higher capacitance value of 100pF in an
extremely compact physical package. This is ideal for lower-voltage
high-capacity decoupling paths in RF bias tees.
Q2: Can I solder directly to the TaN/TiW/Ni/Au electrodes?
A: Yes. The nickel (Ni) barrier layer prevents the gold from leaching
into lead-free or leaded solders during high-temperature reflow,
preserving the integrity of the solder joint.
Q3: What are the storage requirements to prevent bonding failure?
A: Store the capacitors in standard waffle packs or gel-paks inside a
nitrogen cabinet or dry box at 20–25℃ and 40%–60% RH. Under these
conditions, the shelf life is guaranteed for 1 year with pristine
bondability.
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