USRP-LW X310 | Luowave USRP X Series X300 SDR Multiple High Speed Interface

Schematic diagram

High-Performance User-Programmable FPGA

At the heart of the USRP X300, the XC7K325T FPGA provides high-speed connectivity between all major components within the device including radio frontends, host interfaces, and DDR3 memory. The default FPGA core provided with UHD provides all of the functional blocks for digital down-conversion and up-conversion, fine-frequency tuning, and other DSP functions allowing it to be interchangeable with other USRP devices using the UHD architecture. The large Kintex-7 FPGA provides additional space for developers to incorporate custom DSP blocks and is compatible with a large number of USRP supported development frameworks, reference architectures, and open source projects.

Multiple High-Speed Interface Options

The USRP X300 provides multiple interface options. Out of the box, 1 GigE provides a convenient way to get started. For extended bandwidth and lower latency applications such as PHY/MAC research, PCIe x4 provides an efficient bus for deterministic operation. Applications using network recorders or multiple processing nodes can be best served by the 10 GigE interface option.